Electronic systems often include PLL's as a basic building block to stabilize a particular communications channel (keeping it set to a particular frequency), to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency. PLLs are frequently used in wireless communication, particularly where signals are carried using frequency, phase or amplitude modulation. All digital implementations of PLLs are useful for digital data transmission because the circuit blocks are more readily designed and manufactured in the available technologies. For cost, profit and manufacture yield reasons, die area is a premium and there was a need to migrate towards high density, smaller minimum feature size transistor technologies. With today's high density integration process technologies, such as nanometer-scale CMOS, it is possible and easier to process and manipulate digital signals than analog, particularly when the power supply voltage is lower and the signal amplitudes are smaller because digital bits can better overcome signal to noise issues. So an all-digital solution is implemented.
Classically, PLLs are electronic circuits which “predict” the frequency and phase of an input signal by using a voltage or current tunable oscillator that is constantly adjusted to match in phase and/or frequency (and thus lock on) of an input signal. The voltage or current driving the oscillator is representative of the difference in phase and/or frequency of the input signal and the oscillator output is a continually-updated best prediction of the frequency. In the prior-art all-digital implementation, the adjustment is achieved by a closed loop containing various digital circuits, such as shown in example FIG. 1, containing a phase detector (e.g. XOR) to drive a counter indicating the phase difference, the counter to increment or decrement a DCO frequency (digitally controlled oscillator), and the DCO to generate a digital output stream at a frequency that “predicts” the frequency of the input signal going into the phase detector. When the “predicted” frequency matches the frequency of the input signal so that the phase difference is substantially zero, then the ADPLL is in lock.
However, the digital solution has also presented new problems in addition to the generally coarser phase/frequency resolution of prior-art architectures. The new technologies have transistors with large current leakage and power savings became a big problem. Further, an integrated chip for mobile telecommunications in certain standards, such as WCDMA and WLAN, the transceiver circuit block which typically contains a PLL is a larger portion of the entire system. So the current consumption of the PLL (ADPLL) needs to be reduced. Also, noise and spurs created by clocking and synchronizing all the digital circuitry need to be reduced. Performance issues such as better linearity is desired but often difficult to achieve. Finally, lower complexity and lower die area are highly desirable, but again difficult to achieve.
In view of the above issues, there arises a need to address the drawbacks of the prior art digital PLL architectures and circuits, as is achieved by the preferred embodiments described below.